This week Samsung Electronics and Synopsys announced that Samsung has installed its first mobile system-on-chip on Samsung Foundry’s 3nm gate-all-around (GAA) process technology. The announcement, came from Synopsys electronic design automation, further noting that Samsung use Synopsys.ai EDA suite to place and route the layout and verify the SoC design, which in turn enables higher performance.
Samsung’s unnamed high-performance mobile SoC relies on a ‘flagship’ general-purpose CPU and GPU architecture as well as various IP blocks from Synopsys. SoC designers use Synopsys.ai EDA software, including Synopsys DSO.ai to refine designs and maximize throughput as well as the Synopsys Fusion Compiler RTL-to-GDSII solution to achieve higher performance, lower power and optimal area (PPA).
And while the news that Samsung has developed a high-performance SoC using the Synopsys.ai family is a big deal, there’s another, even more important dimension to this announcement: it means that Samsung has finally launched a powerful smartphone application processor in the cut. – 3nm edge GAAFET process.
Although Samsung Foundry has produced GAA-equipped chips SF3E (3nm class, ‘initial’ node) for nearly two years now, Samsung Electronics has not used this technology for its own systems-on-chip for smartphones or other complex devices. To date, SF3E has been used especially for cryptocurrency mining chipspossibly due to the inevitable early growth and yield issues due to the industry’s first commercial GAAFET process.
For now, Samsung isn’t revealing what specific process nodes are used for the SoC; Samsung/Synposys’ official announcement only notes that this is for GAA process nodes. Along with the first generation 3nm class SF3E, Samsung Foundry has a significant advantage more advanced SF3 manufacturing technology which offers many improvements over SF3E, and will be put into mass production in the coming quarters. Given the timing of the announcement, a reasonable possibility is that they’re using SF3.
Regarding Samsung’s tooling partnership with Synopsys, Synopsys tooling was praised for providing some significant performance improvements to chip designs. Specifically, the two companies tout the tools for increasing the chip’s peak clock speed by 300MHz while reducing dynamic power usage by 10%. To achieve this, Samsung Electronics SoC developers used design partition optimization, multi-source clock tree synthesis (MSCTS), and smart wiring optimization to reduce signal interference, as well as a simpler hierarchical approach. And by using Synopsys Fusion Compiler, they did all this while being able to bypass weeks of ‘manual’ design work, according to a joint press release.
“Our long-term collaboration has resulted in a leading SoC design,” said Kijoon Hong, vice president of SLSI at Samsung Electronics. “It is an incredible milestone to successfully achieve the highest performance, power and area on the most advanced mobile CPU core and SoC design in collaboration with Synopsys. We not only showed that AI-based solutions can help us achieve PPA targets even for long-term needs. GAA’s most advanced process technology, but through our partnership, we have built a very high productivity design system that consistently delivers impressive results.”